One increasingly popular application for wireless systems are wireless local area networks (WLANs) of computer systems. Prominent in the field of home and business, wireless computer networks include the wireless standards known as 802.11. The first standard to be available in commercial products was 802.11b. However, increasing demand for higher capacity in the growing wireless LAN market has led to the introduction of a new generation of WLAN standards using more spectrally efficient modulation techniques, including the IEEE 802.11a standard. The 802.11a standard operates in the 5 GHz unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz, 5.725-5.825 GHz) and is based on orthogonal frequency division multiplexing (OFDM). It supports data rates from 6 Mb/s to 54 Mb/s compared to 1 Mb/s to 11 Mb/s offered by 802.11b. The 802.11a operation around 5 GHz offers the additional advantage of less interference compared to the 2.4 GHz ISM band, where in addition to 802.11b, other band users include microwave ovens, cordless phones, Bluetooth systems, and vintage 802.11 systems.
The advantages of 802.11a come at a cost, however, as OFDM-based systems pose significant implementation challenges requiring low in-band phase noise, high linearity, accurate quadrature matching, closely matched frequency response between the I and Q signal paths, and a large dynamic range. “I” and “Q” are terms referring to “in-phase” and “quadrature,” respectively. Ideally, the difference between I and Q signal paths in a transceiver is 90 degrees and the gain is 0 dB. I/Q mismatch refers to the difference in phase and gain between these paths. For example, in order to meet the transmitter error vector magnitude (EVM) specification for the 54 Mb/s mode with a 3 dB implementation margin, system simulation shows that an I/Q mismatch of 1.5°/0.2 dB, an integrated phase noise error of 1°nms and operation at 8 dB backoff from the transmitter 1 dB compression point are required.
In addition to tight performance constraints, pricing pressures require that wireless systems be low-cost and highly integrated implementations. To address these needs, the continuous trend towards low-cost integration of wireless systems has driven the introduction of innovative single-chip architectures in CMOS technologies as inexpensive alternatives to the traditional superheterodyne implementations operating at frequencies up to 5 GHz. Many of these single chip architectures are homodyne or direct conversion architectures, which have much fewer components than superheterodyne implementations. For example, in superheterodyne systems, the intermediate frequency (IF) must be high, so that the image is located far from the wanted signal in the frequency spectrum. However, since the IF frequency is high, the filtering of the desired channel (at IF) must also be done at the high frequency. It is difficult or impossible to implement such a filter as an integrated system, so external components are unavoidable. Direct conversion systems do not need such external components.
However, such highly-integrated direct-conversion single-chip architectures suffer from well-known shortcomings that may limit their applicability. These are problems that are also shared by other integrated architectures such as low-IF or wideband-IF, but which can be further aggravated by using CMOS technology.
For example, on the receiver side, the most common problem is the presence of DC offsets, both static and time-varying. In the 802.11a standard, even though a down-converted I/Q signal occupies bandwidth from 150 kHz to 8.3 MHz, the maximum 40 ppm frequency mismatch allowed between transmitter and receiver may shift the signal around DC, thus prohibiting AC coupling without using complex analog frequency correction techniques.
Static DC offset is the result of component mismatches in the signal path and local oscillator (LO) leakage at the inputs of the mixer and the low-noise amplifier (LNA) due to finite on-chip isolation. The leakage signal after mixing with the LO produces a DC component at the baseband input, which depends on the frequency and power of the LO signal. Since static DC offset may be large enough to saturate the baseband receive chain, it needs to be cancelled in the analog domain.
Time-varying DC offsets, in direct conversion receivers, can be the result of self-mixing due to leakage of single-tone (CW) or frequency modulated (FM) interference to the LO port. Similarly, second order distortion applied to CW or FM interference results in DC offset, which varies with the frequency and the power level of the received signal. Since strong interference is not usually present in the 802.11a operating bands, the dominant mechanism causing time-varying DC offsets is self-mixing of the LO signal leaking to the antenna and reflected back from the environment. At the 5 GHz carrier frequency, due to high attenuation and absorbency of reflected signals, such time-varying DC offsets are small compared to the static DC offsets and the overall dynamic range of the receiver (e.g., in the order of 10-50 mV for a 2Vp-p signal), thus it is well known that the time-varying offsets can be tracked and removed by digital signal processing (DSP) after analog-to-digital conversion.
Direct down/up-conversion from/to 5 GHz requires quadrature LO generation at the RF carrier frequency which may result in large I/Q mismatches (including gain and phase mismatches). Other significant problems include sensitivity to flicker noise and pulling of the voltage-controlled oscillator (VCO) by the external or on-chip power amplifier (PA). In addition to these architecture-related non-idealities, higher order QAM-OFDM modulation requires tightly matched baseband I/Q filters on both transmit and receive side to avoid degradation of the overall EVM.
Some of the aforementioned problems and requirements can be mitigated and addressed by careful circuit design and layout, analog auto-calibration techniques or one-time calibration at production testing. However, such approaches may require several design iterations and can be highly sensitive to process variations, thus degrading yield and increasing overall cost, which may cancel the advantages of using CMOS integrated architectures.
Accordingly, what is needed is a low-cost system and method for implementing a highly-integrated direct-conversion transceiver, including CMOS implementations, with the aforementioned problems eliminated or minimized. The present invention addresses such needs.